Clock generation circuit with fast-startup standby mode

ABSTRACT

A clock generation circuit operates in a STANDBY mode as well as conventional OFF and ON modes. In STANDBY mode, a small pre-bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to very near their operating voltage values. This reduces transient perturbations on signals as the clock generation circuit is returned to ON mode. The smaller transients settle faster, and allow the clock generation circuit to achieve very fast startup times from STANDBY to ON. The very fast startup times allow the clock generation circuit to be placed in STANDBY mode more often, such as when a system must monitor and rapidly respond to activity on an external bus or interface (such as an RF modem).

This present application is a reissue application of U.S. Ser. No.14/690,753, filed Apr. 20, 2015, which issued on Nov. 1, 2016 as U.S.Pat. No. 9,484,893.

FIELD OF INVENTION

The present invention relates generally to clock generation circuits,and in particular to a clock generation circuit having a standby modefeaturing low power consumption and fast start-up time.

BACKGROUND

Portable electronic devices are ubiquitous accoutrements in modern life.Cellular telephones, smartphones, satellite navigation receivers, e-bookreaders and tablet computers, wearable computers (e.g., glasses, wristcomputing), cameras, and music players are just a few examples of themany types of portable electronic devices in widespread use. Portableelectronic devices are powered by batteries—either replaceable batteriessuch as alkaline cells, or rechargeable batteries such as NiCd, NiMH,LiOn, or the like. In either case, the useful life of portableelectronic devices is limited by available battery power, whichdecreases in proportion to the length of use of the device, and thelevel of power consumption during that use.

Trends in portable electronic device design exacerbate the problem oflimited available power. First, device form factors tend to shrink, dueto increasing integration of electronics and miniaturization ofcomponent parts, such as disk drives. This forces the size of thebattery to shrink as well, which generally reduces the available energystorage capacity. Second, electronic devices are increasinglysophisticated, offering new applications, more sophisticated userinterfaces, enhancements such as encryption, and the like. Theadditional software implementing these features requires increasedcomputational power to execute, which translates to larger, oradditional, processors and more memory. Finally, successive generationsof portable electronic device often add additional features such asvarious modes of wireless connectivity, which may require theintegration of additional chip sets and other electronics. An increasein the demand for power by more processors and circuits, coupled withever-shrinking battery size and capacity, has made power management acritical area of optimization for portable electronic device designers.

Several approaches to power management are known in the art. One suchapproach is to identify circuits (or sub-circuits) that are not used forextended periods, and put them into a low-activity state, also referredto as a “sleep” mode, even if other circuits in the device are fullyactive. As one example, the illuminated display screen of many deviceswill shut off after a (selectable) duration of no user interactivity.One way to shut down digital circuits is to isolate clocks signals fromthese circuits. Since storage elements within the digital circuits onlychange state in response to clock signal edges or levels,power-consuming electrical activity within the circuits effectivelyceases.

A more sophisticated approach to the “sleep” technique is to match thefrequency of a clock signal to the level of activity of a digitalcircuit. For example, a processor engaged in heavy computation may beclocked at a high frequency, to extract maximum performance. However,when the processor is performing merely background tasks, the frequencyof its clock signal may be reduced without a user-noticeable degradationof performance, which concomitantly reduces the power consumed.

Another approach to power management is to vary the power supplied tovarious circuits (or sub-circuits) according to the instantaneous loadof the circuit. In this manner, circuits that are engaged in computationor other activity are provided sufficient power to operate, and circuitsexperiencing a lighter load are provided with a lower level of current.

All of these power management techniques are problematic when applied toa wireless modem 58, as depicted in FIG. 22, which may include a digitalbroadband integrated circuit (IC) 60, radio frequency IC 62, and poweramplifier 64. When a user is actively using the data connection andexpecting high download speed and short latency, the modem 58 isconfigured with highest performance settings, such as high speed clocks,full power, and all circuits enabled. When the data connectionrequirements are relaxed, there is an opportunity to save power bylowering the wireless modem 58 performance, such as by lowering clockfrequencies, gating clocks to some circuits, lowering supply voltages,and shutting down circuits that are not used. Such wireless modem 58throttling is limited by the fact that the user may resume dataconnection usage at any time, and the wireless modem 58 must return froma power-saving mode to full performance, without user-perceptible delay.This means that the wireless modem 58 has a few tens of milliseconds toresume from a power-saving mode to a high performance mode.

When the wireless modem enters a limited performance or power-savingmode, voltage regulators may be configured to a mode where outputcurrent capability is limited. Another power-saving measure is to limitclock signal distribution to switching mode analog blocks (e.g.,Switched Mode Power Supply) by digital control such as clock gating, oreven disabling the clock generation circuit completely. Disabling theclock generation circuit achieves the best power savings, but it can bedone only when none of the wireless modem circuits require a clocksignal. Another constraint is that the clock generation circuit musthave a start-up time fast enough to satisfy the full power transitiontime requirements of all blocks receiving the clock signal(s).

New generations of wireless modem design simultaneously require higherfrequency and reduced power consumption. For example, a 6.5 MHz controlbus is targeted, in future designs, to operate at 26 MHz. One approachto reaching these challenging design goals is to enter restricted-clock,or “sleep” mode more often. However, this requires a very fast start-uptime from the dormant state, such as 1.5 u-sec, compared to currentdesigns of 10 u-sec.

A large challenge to designing a clock generation circuit with a faststart-up time, but which consumes little power during operation, is thatRC factors are large and bias currents are small. As intermediate nodesbegin to charge from ground (or supply voltage), they not only chargeslowly but also it takes time for transient perturbations in the nodevoltages to settle. Settling of the node voltages at the properoperating values is essential to achieve an accurate clock signal.

Known approaches to decreasing the clock generation circuit start-uptime include boosting bias currents, disconnecting capacitors, andtransferring target voltages directly to intermediate and output nodes.All of these approaches suffer from the deficiency that onceintermediate circuit nodes are charged, it still takes time to settlethe node voltage sufficiently to achieve frequency stability.Accordingly, the known approaches are insufficient to reduce clockgeneration circuit start-up time by the necessary amount.

Korean Patent Publication No. KR-20050074755 by K. Han, titled “Lowpower relaxation oscillator circuit,” describes a boost circuit thatinjects current into both nodes n1 and n2 of the capacitor C of arelaxation oscillator.

The paper by T. Tokairin, et al., titled, “A 280 nW, 100 kHz, 1-CycleStart-up Time, On-chip CMOS Relaxation Oscillator Employing aFeedforward Period Control Scheme,” published in the 2012 Symposium onVLSI Circuits Digest of Technical Papers, p. 16, describes a scheme toshift the oscillator switching delay to prior to a comparator reaching areference voltage as the capacitor charges. This is accomplished bydoubling the charging current at the beginning of every half cycle ofoscillation, which the authors refer to as “boost charging.”

U.S. Pat. No. 7,005,933 to J. Shutt describes a dual mode relaxationoscillator that generates clock signals in both normal and low-powermode, with the clock in low-power mode being less accurate.

U.S. Pat. No. 4,250,464 to O. Schade describes a multi-mode relaxationoscillator which generates a lower frequency clock signal in low-powermode than in normal operating mode.

The Application note AN9334.2 published by Intersil Corporation, titled“Improving Start-up Time at 32 KHz for the HA7210 Low Power CrystalOscillator,” December 2000, describes a crystal oscillator having anenable pin operative to turn off an output buffer in stand-by mode tosave power. The internal oscillator continues to run in stand-by mode.Power savings are limited to 50%.

None of these prior art solutions can achieve a high frequency clockgeneration circuit having a low-power mode with approximately 90% powerconsumption reduction, yet with very short start-up time to return tofull operating mode of approximately 1.5 u-sec.

The Background section of this document is provided to place embodimentsof the present invention in technological and operational context, toassist those of skill in the art in understanding their scope andutility. Unless explicitly identified as such, no statement herein isadmitted to be prior art merely by its inclusion in the Backgroundsection.

SUMMARY

The following presents a simplified summary of the disclosure in orderto provide a basic understanding to those of skill in the art. Thissummary is not an extensive overview of the disclosure and is notintended to identify key/critical elements of embodiments of theinvention or to delineate the scope of the invention. The sole purposeof this summary is to present some concepts disclosed herein in asimplified form as a prelude to the more detailed description that ispresented later.

According to one or more embodiments described and claimed herein, aclock generation circuit operates in a STANDBY mode as well asconventional OFF and ON modes. In STANDBY mode, a small bias current isapplied to amplifiers in the clock generation circuit, which biasvoltages on internal nodes to very near their operating voltage values(i.e., in ON mode). This reduces transient perturbations on signals asthe clock generation circuit is returned to ON mode. The smallertransients settle faster, and allow the clock generation circuit toachieve very fast startup times from STANDBY to ON—for example, in therange of 15% of startup time from OFF to ON (i.e., 1.5 usec as comparedto 10 usec). The very fast startup times allow the clock generationcircuit to be placed in STANDBY mode more often, such as when a systemmust monitor and rapidly respond to activity on an external bus orinterface (such as an RF modem). The small bias current applied inSTANDBY mode may be in the range of 10% of the bias current applied tothe clock generation circuit in ON mode.

One embodiment relates to a method of operating a clock generationcircuit on an integrated circuit, the clock generation circuit includingan oscillator circuit. Clock request indicators from one or morecircuits are monitored. If at least one circuit requests a clock signal,the clock generation circuit is operated in a first, full power mode inwhich the clock generation circuit outputs at least one clock signal. Ifno circuit requests a clock signal, it is determined whether a second,sleep mode is allowed, in which the oscillator circuit is disabled andthe clock generation circuit outputs no clock signal. If the second,sleep mode is allowed, the clock generation circuit is operated in thesecond, sleep mode. If the second, sleep mode is not allowed, the clockgeneration circuit is operated in a third, standby mode in which one ormore circuit nodes in the clock generation circuit are biased near theiroperating voltages but the oscillator circuit does not oscillate and theclock generation circuit outputs no clock signal.

Another embodiment relates to a clock generation circuit. The clockgeneration circuit includes an oscillator circuit operative toselectively generate a periodic signal. The clock generation circuitalso includes an output circuit receiving a periodic signal from theoscillator circuit and operative to selectively output at least oneclock signal. The clock generation circuit further includes a biascircuit operative to control the clock generation circuit to operate inone of three modes, selected from the group consisting of a first, fullpower mode in which the output circuit outputs at least one clocksignal; a second, sleep mode in which the oscillator circuit is disabledand the output circuit outputs no clock signal; and a third, standbymode in which nodes within the oscillator circuit and output circuit arebiased near their operating voltages but the oscillator circuit does notoscillate and the output circuit outputs no clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. However, this invention should not be construed aslimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the invention to those skilled in theart. Like numbers refer to like elements throughout.

FIG. 1 is a functional block diagram of some circuits in a portableelectronic device.

FIG. 2 is a flow diagram of a method of providing system power.

FIG. 3 is a functional schematic diagram of one embodiment of a clockgeneration circuit.

FIG. 4 is a timing diagram showing system operational states and controlsignals.

FIG. 5 is a qualitative graph of current consumption vs. startup timefor a clock generation circuit.

FIG. 6 is a functional block diagram of a relaxation oscillator.

FIG. 7 is a functional schematic diagram of the current generation andintegration circuits of the oscillator of FIG. 6.

FIG. 8 is a functional block diagram of a relaxation oscillator,identifying the points of transient instability.

FIG. 9 is a functional block diagram of a relaxation oscillatoraccording to one embodiment of the present invention.

FIG. 10 is a functional schematic diagram of the current generation andintegration circuits of the oscillator of FIG. 9.

FIG. 11 is a functional schematic diagram of the scaling and bufferingcircuit of the oscillator of FIG. 9.

FIG. 12 is a functional schematic diagram of the comparison circuit ofthe oscillator of FIG. 9.

FIG. 13 is a functional transistor level schematic diagram of thecurrent generation and integration circuits of a relaxation oscillatorin the OFF state.

FIG. 14 is a functional transistor level schematic diagram of thecurrent generation and integration circuits of FIG. 13 in the ON state.

FIG. 15 is a functional transistor level schematic diagram of thecurrent generation and integration circuits of a relaxation oscillatorin a STANDBY state.

FIG. 16 is a functional transistor level schematic diagram of thecurrent generation and integration circuits of FIG. 15 in the ON state.

FIG. 17A is a graph of reference current transients and bias current inthe circuit of FIGS. 13 and 14.

FIG. 17B is a graph of reference current transients and bias current inthe circuit of FIGS. 15 and 16.

FIG. 18 is a functional transistor level schematic diagram of thecharging voltage generation circuit of a relaxation oscillator in theOFF state.

FIG. 19 is a functional transistor level schematic diagram of thecharging voltage generation circuit of FIG. 18 in the ON state.

FIG. 20 is a functional transistor level schematic diagram of anothercharging voltage generation circuit of a relaxation oscillator in theSTANDBY state.

FIG. 21 is a functional transistor level schematic diagram of thecharging voltage generation circuit of FIG. 20 in the OFF state.

FIG. 22 is a block diagram of a wireless modem.

DETAILED DESCRIPTION

For simplicity and illustrative purposes, the present invention isdescribed by referring mainly to an exemplary embodiment thereof. In thefollowing description, numerous specific details are set forth in orderto provide a thorough understanding of the present invention. However,it will be readily apparent to one of ordinary skill in the art that thepresent invention may be practiced without limitation to these specificdetails. In this description, well known methods and structures have notbeen described in detail so as not to unnecessarily obscure the presentinvention.

FIG. 1 depicts portions of a representative system 10 in a portableelectronic device. The system 10 includes a Power Management Unit (PMU)12 and an electronic circuit 20, such as the baseband processing systemof a wireless communication terminal. A digital baseband circuit is theheart of a wireless modem in a communication terminal, receivingbaseband data from an RF transceiver (not shown) and decoding user datafrom it, as well as encoding user data and sending it to the RFtransceiver to be transmitted over the air.

The PMU 12 includes a clock generation circuit 14, a Switched Mode PowerSupply 16, and a control circuit 18. The clock generation circuit 14generates one or more clocking signals to drive the power transferswitches in the SMPS 16, which regulates and transfers power (e.g., froma battery) to the digital or analog electronic circuit 20, and othercircuits (not shown). Thus, suspending the operation of the clockgeneration circuit 14 will shut down power supplied to the electroniccircuit 20.

The electronic circuit 20 includes a power controller circuit 22, andmay include various digital or analog circuits, such as a processor 24and/or Digital Signal Processor (DSP) 26, and a high speed interface 28,such as to memory, an external bus, a wireless transceiver, or the like.The power controller circuit 22 may communicate with the PMU controlcircuit 18 via a serial interface such as I2C or SPMI. The PMU 12 thusreceives clock requests and commands from the power control circuit 22,and controls circuits on the PMU 12 in response, such as adjusting biasvoltages and currents, enabling/disabling clock drivers, adjusting theduty cycle of the SMPS 16 switching, and the like. Only the controlsignals relevant to discussion of embodiments of the present inventionare shown; those of skill in the art will recognize that the circuitsdepicted may interact via numerous other control, clock, power, andsimilar signals. Accordingly, those of skill in the art will readilyrecognize that the block diagram of FIG. 1 is representative only, andis no way limiting regarding the application of embodiments of thepresent invention.

To preserve battery power, one or more of the circuits 24, 26, 28 may beplaced into “sleep” mode, by reducing or eliminating the power suppliedto the circuit 24, 26, 28, or by suspending the clock signals suppliedto a digital circuit. One straightforward way to suspend power from theSMPS 16 is to halt the clock signal from the clock generation circuit 14that drives the SMPS 15 energy transfer switches. The clock signal maybe suspended by gating off the output of the clock generation circuit14, while leaving its internal oscillator running. This allows forfaster start-up time, but is less efficient as the clock generationcircuit 14 continues to consume power. For greater power savings, when along startup time can be tolerated, the entire clock generation circuit14, including its oscillator, may be shut down. Accordingly, known clockgeneration circuits have two operational states: ON and OFF.

According to one or more embodiments described herein, a clockgeneration circuit 14 has three operational states or modes: ON, OFF,and STANDBY. During STANDBY mode, certain intermediate circuit nodesinternal to the clock generation circuit 14 are charged to a targetvoltage with a small bias current, referred to herein as a pre-bias. Thepre-bias current can be scaled to a minimal value, e.g., in the range of10% of the clock generation circuit ON mode bias current. Simulations ofembodiments reveal an improvement in startup time from STANDBY to ONmodes of 1.5 usec, as opposed to the OFF to ON startup time of 10 usec.Although the clock generation circuit 14 consumes some current inSTANDBY mode, the faster startup time allows the system 10 to disablethe clock generation circuit 14 more often, as compared to conventionalclock generation circuits, with their longer OFF to ON startup time.

FIG. 2 depicts an overall method 100 of delivering power to anelectronic circuit 20, such as a digital baseband system, in a portableelectronic device. Initially, the PMU 12 is powered on (block 102). ThePMU 12 performs a start-up sequence, which includes powering ON a clockgeneration circuit 14, and conditioning the clock generation circuit 14output to generate one or more clock signals (block 104). The clocksignals may, for example, provide a switching signal for the SMPS 16that deliver power to the other electronics 20 in the system 10. After arelatively long startup duration (e.g., 10 usec), the clock generationcircuit 14 is in an ON state (block 106).

As long as at least one circuit 16, 24, 26, 28 or module in the system10 requests a clock signal (block 108), the clock generation circuit 14remains ON (block 106). In the event that all relevant electroniccircuits 16, 24, 26, 28 are placed in a “sleep” mode to preserve power(block 108), the method 100 checks whether the clock generation circuit14 may be fully disabled (block 110). This may comprise, for example,checking the state of one or more status bits in a status register orother predefined memory location. In use cases where a fast startup timeis not critical, and maximum power savings are desired, the PMU 12 turnsthe clock generation circuit 14 OFF (block 112). The clock generationcircuit 14 remains OFF until a circuit 16, 24, 26, 28 requests a clocksignal (block 114), when the clock generation circuit 14 is turned ON(block 105 106) and power and clocks are supplied. This transition(block 112 to 106) incurs a significant delay.

When it is again decided to place the system 10 in sleep mode (block108) but a fast startup time is required (e.g., to respond to activityon an external bus, to process an incoming wireless signal, or thelike), the status information (block 110) may indicate that the PMU 12may place the clock generation circuit 14 in STANDBY mode (block 116).In STANDBY mode, the clock generation circuit 14 does not generate anoutput; however, a voltage is maintained on internal nodes by a smallpre-bias current. Because of the pre-bias current, when a circuit 24,26, 28 again requests a clock signal (block 118), the clock generationcircuit 14 may exit STANDBY and be fully ON (block 106) and operationalin a very short startup time (e.g., 1.5 usec). The fast startup timeenables greater use of STANDBY mode, reducing overall power consumption.

FIG. 3 depicts one embodiment of a clock generation circuit 14. Theclock generation circuit 14 includes an RC oscillator 30, clock qualityanalyzer 32, AND gate function 34, and output driver 36. As well knownin the art, the op amp in the RC oscillator 30 will generate a periodicoutput signal, the frequency of which depends on the values of thecapacitor C and resistor R, when a bias driver 38 powers up theoscillator 30 op amp, and provides a relatively large bias current. Aclock quality analyzer circuit 32 monitors the oscillator 30 output, andwill only output a “1” toward the AND function 34 when the clock signalmeets predetermined quality specifications regarding voltage, frequency,jitter, ripple, duty cycle, and the like. The AND gate function 34allows the RC oscillator 30 output to pass to the output buffer 36 onlyif the ClockRequest input is asserted, and the clock quality analyzercircuit 32 determines that the clock signal is within specification. Inconventional clock generation circuits, the clock quality analyzercircuit 32 may suspend the clock signal for 10 usec or more, intransitioning from OFF to ON.

According to embodiments of the present invention, a StandBy inputsignal triggers a pre-bias driver 40 to provide a lower, pre-biascurrent to the amplifier in the RC oscillator 30 when the oscillator 14is in STANDBY mode. The pre-bias current keeps the amplifier charged,but is insufficient to enable oscillation. When the ClockRequest signalis asserted, full bias is established and the RC oscillator 30 startsup, quickly settling to the proper output point, generating a highquality clock signal at the correct frequency. The clock qualityanalyzer circuit 32 verifies this, and rapidly enables the AND gatefunction 34 to pass the clock signal to the output buffer 36.

FIG. 4 is a timing diagram depicting the operational state of the system10 and the clock generation circuit 14, as well as control signalsStandBy and ClockRequest. Initially, the system 10 (including the clockgeneration circuit 14) is OFF. Upon power-up, the system 10 is in aSTARTUP state during which various circuits 12, 20 power up andinitialize. During this time, the clock generation circuit 14transitions from OFF to ON states, as indicated by the relatively longhashed startup time. Generally, the clock generation circuit 14 startuptime is not the critical system startup parameter, as other circuits(e.g., processors 24, 26) have much longer initialization/boot-upsequences.

Once all circuits initialize, the clock generation circuit 14 providesat least one clock signal to the SMPS 16, which provides power tocircuits 24, 26, 28. The system 10 is in ACTIVE state. When operationalconditions permit, for power conservation purposes the system 10 goesinto SLEEP mode, and the clock generation circuit 14 is placed inSTANDBY. This occurs because ClockRequest is deasserted, indicating nocircuit 16, 24, 26, 28 requires clock signals. However, the StandBysignal remains asserted. This causes a pre-bias current to be applied tothe RC oscillator circuit 30 within the clock generation circuit 14,almost fully charging the amplifier and maintaining the output node atnear its operational voltage. When the system 10 exits SLEEP mode byagain asserting ClockRequest, only a very short startup time is requiredto transition the clock generation circuit 14 from STANDBY to ON. Thistranslates to a corresponding brief duration in which the system 10transitions from SLEEP to ACTIVE mode.

FIG. 5 is a qualitative graph depicting the relationship between currentconsumption and startup time for each of the three operating modes ofthe clock generation circuit 14. When the clock generation circuit 14 isON, there is no problem with startup time; however, the currentconsumption is at a maximum. When the clock generation circuit 14 is OFFthere is zero current consumption, but the startup time is long. TheSTANDBY mode provides a compromise. The power consumption is only 1/10that during the fully ON state, and while the startup time is not zero,it is only 1/7 the time required to transition out of the OFF state. Foruse cases where tight startup time requirements preclude turning theclock generation circuit 14 fully OFF, the STANDBY mode provides anadditional way to save 90% of the power, while still satisfying startuptime requirements.

The clock generation circuit 14 depicted in FIG. 3 is based on an RCoscillator 30. A more complex, and more commonly deployed, form of clockgeneration circuit 14 employs a relaxation oscillator, depicted in blockdiagram form in FIG. 6. A relaxation oscillator operates by repeatedlycharging and discharging an integration capacitor via a feedback loop.

A bandgap reference circuit 40 generates a reference voltage Vref, andprovides it to both a scaling/buffering circuit 42 and the currentgeneration circuit 44. The scaling and buffering circuit 42 scales andbuffers the reference voltage Vref, outputting a steady thresholdvoltage Vth. The current generation with trimming circuit 44 generates acharging current Icharge, which charges an integration capacitor in anintegration circuit 46. As indicated by the dashed-line box, the currentgeneration circuit 44 and integration circuit 46 are tightly coupled.

The integration circuit 46 outputs a saw-tooth integrated voltage Vint,which increases as the integration capacitor charges and returns to zerowhen the capacitor discharges. A comparison circuit 50 compares theintegrated voltage Vint to the threshold voltage Vth, and generates areset impulse when they are equal. The reset signal is fed back to theintegration circuit 46, as a trigger to discharge the integrationcapacitor. The integration capacitor then begins charging again togenerate the next cycle. A shaping and buffering circuit 52 conditionsthe saw-tooth wave of the integrated voltage Vint, outputting a squareclock signal Clock. The frequency of the Clock signal is determined bythe threshold voltage Vth and the magnitude of the current Icharge,which directly controls the charging time of the integration capacitor.

FIG. 7 depicts a conventional implementation of the current generationcircuit 44 and integration circuit 46. A trim code applied to the chainof resistors sets the resistance in the current generating path 44(i.e., through transistor M1, the gate of which is controlled by theamplifier 45), thus controlling the current through this path. A currentmirror comprising matched transistors M2 and M3 copies this current to aproportional charging current Icharge in the integration path 46, whereit charges the integration capacitor Cint. The integration circuit 46outputs the integrated voltage Vint as the voltage across the capacitorCint. The reset signal received in feedback from the comparison circuit50 discharges the capacitor to begin the next charging iteration. Whenthe ClockRequest=0 to place the clock generation circuit 14 in OFFstate, the gates of the current mirror are pulled high, shutting offboth transistors and halting the charging current flow. When thesecircuits 44, 46 are again turned ON, transients at the output of theamplifier 45 must settle before a stable charging current Icharge isreestablished, which is necessary for frequency-stable clock generation.

However, the current generation circuit 44 and integration circuit 46are not the only sources of startup transients that cause a lengthystartup time in transitioning the clock generation circuit 14 from OFFto ON. FIG. 8 depicts transients in the threshold voltage Vth caused bythe amplifier startup. Additionally, the charging current Ichargeexperiences transients. Furthermore, transients appear in the biasing ofthe comparator in the comparison circuit 50. All of these transientsmust settle, and the relevant nodes reach a steady-state voltage, beforea clock signal can be output.

As indicated in FIG. 9, according to embodiments of the presentinvention, the StandBy signal is distributed to the scaling andbuffering circuit 42, the current generation circuit 44, the integrationcircuit 46, and the comparison circuit 50, and the shaping and bufferingcircuit 52. When ClockRequest=0 but StandBy=1, the clock generationcircuit 14 enters a STANDBY mode, in which pre-bias currents aresupplied to amplifiers in the clock generation circuit 14 to reducestartup transients, and hence startup time, when the clock generationcircuit 14 is turned fully ON.

FIG. 10 depicts the current generation circuit 44 and integrationcircuit 46 in STANDBY mode, according to one embodiment. As with theprior art circuit of FIG. 7, ClockRequest=0 pulls the gates of themirror current transistors M2, M3 high, turning M3 off and makingIcharge=0 in the integration circuit 46. The amplifier 45 receives a lowpre-bias current. Logic in the current generation circuit 44 replacesthe trim resistors with a series of diode-connected transistors whenClockRequest=0 AND StandBy=1. In this configuration, both the amplifier45 and the transistor M1 are biased very close to their operatingpoints. M1 can then return to full conduction very rapidly whenClockRequest=1, with low transients that quickly settle, yielding a veryshort startup time to a stable clock output.

FIG. 11 depicts the StandBy input providing a pre-bias current to thecomparator amplifier in the scaling and buffering circuit 42 duringSTANDBY mode. This biases the amplifier to near its operational point.The values of resistors R1 and R2 are increased so that the amplifierwith lower biasing can drive them. Higher resistor values are notproblematic since the threshold voltage Vth is always constant and thereis no need to settle fast. The amplifier bias is increased when theclock generation circuit 14 is turned ON so that the threshold voltageVth is more stable, even when the comparator is switching.

FIG. 12 depicts the StandBy input providing a pre-bias current to thecomparator amplifier in the comparison circuit 50 during STANDBY mode.This biases the amplifier to near its operational point. The amplifierbias is increased when the clock generation circuit 14 is turned ON sothat the comparator can switch rapidly enough.

FIGS. 13-16 depict transistor-level views of various embodiments of thecurrent generation circuit 44 and integration circuit 46 of therelaxation oscillator of a clock generation circuit 14. For clarity, asingle control signal “enable” and its inverse “disable” are showncontrolling switches. The enable/disable signals result from theClockRequest signal described above (and possibly other system logic).

FIG. 13 depicts a conventional circuit, in which the clock generationcircuit 14 is OFF. FIG. 14 depicts the same circuit in the ON state. Thecurrent generation path 44 includes transistors M2, M1, and the variable(trim) resistors. An amplifier 45 drives the gate of M1. A bias currentcircuit 47 provides additional current Ibias to the amplifier 45, in theON state.

FIG. 13 depicts the clock generation circuit 14 in the OFF state. Thetransistor M1 is isolated, with no current flowing through the variableresistance R to generate current in the current generating path 44.Thus, no charging current Icharge flows in the integration path 46 tocharge a capacitor (not shown). The amplifier 45 is disabled, and itsinverting input is grounded. The bias current circuit 47 is disabled.

FIG. 14 depicts the same circuits in the ON state. The transistor M1 isconnected to both M2 and the resistors R, generating current in the path44, which is mirrored in the integration path 46 as Icharge. Theamplifier 45 is enabled, its inverting input is connected to the sourceof M1, and a bias current Ibias is applied to the amplifier 45 by thebias circuit 47. Because Ibias goes from zero to its full value when theoscillator 14 is switched ON, transients at the output of the amplifier45 require several microseconds to stabilize.

FIGS. 15 and 16 depict similar circuits, but in which a small biascurrent Ibias/10 is continuously applied to the amplifier 45. That is,FIG. 15 depicts the clock generation circuit 14 in STANDBY mode, andFIG. 16 shows it in the fully ON state.

In FIG. 15, the amplifier 45 is enabled, and its inverting input isconnected to the current generation path 44, in which a small currentflows through M1 and the chain of diodes. A small bias current Ibias/10is continuously applied to the amplifier 45 by the bias circuit 47. Thiskeeps the amplifier 45 biased very close to its operating point.

In FIG. 16, the clock generation circuit 14 is switched ON, and the trimresistors R are switched into the current generating path 44. Chargingcurrent Icharge is established in the integration path 46. The amplifier45 is fully enabled, and Ibias/10 is continuously applied by the biascircuit 47.

FIG. 17A is a graph of transients on Icharge and the bias current Ibiasas the clock generation circuit 14 switches from OFF to ON. FIG. 17Bdepicts the same for transitioning the clock generation circuit 14between STANDBY and ON modes. With constant bias (i.e., the STANDBYmode), the bias points of the amplifier 45 are almost constant all thetime, and therefore the transients are much smaller. They also settlefaster, allowing for a faster startup time. Additionally, the biascurrent can be much lower (e.g., in the range of 10% of the full biascurrent).

FIGS. 18-21 depict transistor-level views of other embodiments of thecurrent generation circuit 44 and integration circuit 46 of a relaxationoscillator in a clock generation circuit 14, wherein the integrationcircuit generates a integration capacitor charging voltage Vchargerather than the reference current Icharge described above. FIGS. 18 and19 depict the case of switched biasing, where the clock generationcircuit 14 is in OFF and ON states, respectively. FIGS. 20 and 21 depictthe same circuit with constant biasing, where the clock generationcircuit 14 is in STANDBY and ON states, respectively.

In FIG. 18, the current generating path 44 and amplifier 45 aredisabled, and no current flows through the variable (trim) resistors.The bias current circuit 47 is also disabled. Vcharge=0, so theintegration capacitor (not shown) does not charge/discharge to generatea Clock signal.

In FIG. 19, the current generating path 44 and amplifier 45 are enabled,and current through the variable (trim) resistors generates a chargingvoltage Vcharge. The bias circuit 47 is enabled, providing a biascurrent Ibias to the amplifier 45.

FIG. 20 depicts an embodiment where a partial bias is applied to theamplifier 45, when the clock generation circuit 14 is in STANDBY mode.No current flows through the variable (trim) resistors, so Vcharge=0.However, the amplifier 45 is enabled and the bias circuit 47 applies apartial bias current. Note that transistor 49 is disabled, limiting thebias current to only that required to bias the amplifier 45 to near itsoperating point.

FIG. 21 depicts the clock generation circuit 14 in fully ON state.Current flowing through the variable (trim) resistors generates acharging voltage Vcharge. The amplifier 45 is fully on, and the biascurrent circuit 47 provides both the standby bias current, andadditionally enables transistor 49, providing additional bias current.This additional bias current during operation helps the amplifier 45deal with transient loads.

In all of the embodiments described above, a clock generation circuit 14transitions from a STANDBY mode, in which a small, pre-bias current isapplied to amplifiers, to a fully ON state, with fewer transients, whichquickly settle to a steady-state. Hence, the clock generation circuit 14startup time is dramatically shorter than in prior art designs, whichonly transition the clock generation circuit 14 between OFF and ONstates. The pre-bias current consumption in the STANDBY state is small,such as in the range of 10% of the bias current applied in the ON state.The very fast startup time allows the clock generation circuit 14 to beplaced in STANDBY more often than conventional circuits, thus reducingoverall power consumption, despite the small pri-bias currentconsumption in the STANDBY state. For example, the clock generationcircuit 14 may be placed in STANDBY mode when an external bus orwireless interface is dormant, but may become active at any time,requiring e.g., the capture of burst data transfers.

The STANDBY bias current circuits disclosed herein are straightforward.As such, they are robust on silicon variation, and portable betweensilicon technologies. Additionally, by providing a very short startuptime from STANDBY to ON, designers may optimize the ON mode powerconsumption and performance, without concern for startup performance.

The present invention may, of course, be carried out in other ways thanthose specifically set forth herein without departing from essentialcharacteristics of the invention. The present embodiments are to beconsidered in all respects as illustrative and not restrictive, and allchanges coming within the meaning and equivalency range of the appendedclaims are intended to be embraced therein.

What is claimed is:
 1. A method of operating a clock generation circuiton an integrated circuit, the clock generation circuit including anoscillator circuit, comprising: monitoring clock request indicators fromone or more circuits; if at least one circuit requests a an associatedclock signal, operating the clock generation circuit in a first, fullpower mode in which the clock generation circuit outputs at least oneclock signal; if no circuit requests a an associated clock signal,determining whether a second, sleep mode is allowed, in which theoscillator circuit is disabled and the clock generation circuit outputsno clock signal; if the second, sleep mode is allowed, operating theclock generation circuit in the second, sleep mode; if the second, sleepmode is not allowed, operating the clock generation circuit in a third,standby mode in which one or more circuit nodes in the clock generationcircuit are biased near their operating voltages but the oscillatorcircuit does not oscillate and the clock generation circuit outputs noclock signal.
 2. The method of claim 1 further comprising, when theclock generation circuit is in the third, standby mode: detecting atleast one clock request indication; in response to detecting at leastone clock request indication, transitioning the clock generation circuitfrom the third, standby mode to the first, full power mode; wherein astart-up time from detecting at least one clock request indication tooutputting a stable clock signal is less than 10 usec.
 3. The method ofclaim 2 wherein the start-up time is less than 2 usec.
 4. The method ofclaim 1 wherein power consumption of the clock generation circuit in thethird, standby mode is at least 50% less than in the first, full powermode.
 5. The method of claim 4 wherein power consumption of the clockgeneration circuit in the third, standby mode is at least 90% less thanin the first, full power mode.
 6. The method of claim 1 wherein theclock generation circuit has separate first and second enable inputs,and wherein operating the clock generation circuit in the first, fullpower mode comprises asserting both first and second enable signalsapplied to the first and second enable inputs, respectively; operatingthe clock generation circuit in the second, sleep mode comprisesdeasserting both of the first and second enable signals; and operatingthe clock generation circuit in the third, standby mode comprisesasserting the first enable signal and deasserting the second enablesignal.
 7. The method of claim 1 wherein operating the clock generationcircuit in the first, full power mode comprises providing a first biascurrent to the clock generation circuit; operating the clock generationcircuit in the second, sleep mode comprises providing no bias current tothe clock generation circuit; and operating the clock generation circuitin the third, standby mode comprises providing a second bias current,less than the first bias current, to the clock generation circuit. 8.The method of claim 7 wherein the second bias current is about 10% ofthe first bias current or less.
 9. The method of claim 1 wherein theoscillator circuit is an RC oscillator.
 10. The method of claim 1wherein the oscillator circuit is a relaxation oscillator.
 11. A clockgeneration circuit, comprising: an oscillator circuit operative toselectively generate a periodic signal; an output circuit receiving athe periodic signal from the oscillator circuit and operative toselectively output at least one clock signal; a bias circuit operativeto control the clock generation circuit to operate in one of threemodes, selected from the group consisting of a first, full power mode inwhich the output circuit outputs the at least one clock signal; asecond, sleep mode in which the oscillator circuit is disabled and theoutput circuit outputs no clock signal; and a third, standby mode inwhich nodes within the oscillator circuit and output circuit are biasednear their operating voltages but the oscillator circuit does notoscillate and the output circuit outputs no clock signal.
 12. The clockgeneration circuit of claim 11 further comprising at least one controlinput, and wherein, in response to one or more signals received at theat least one control input, the clock generation circuit is operative totransition from the third, standby mode to the first, full power mode,and wherein a start-up time from the one or more control signals tooutputting a stable clock signal is less than 10 usec.
 13. The clockgeneration circuit of claim 12 wherein the start-up time is less than 2usec.
 14. The clock generation circuit of claim 11 wherein powerconsumption of the clock generation circuit in the third, standby modeis at least 50% less than in the first, full power mode.
 15. The clockgeneration circuit of claim 14 wherein power consumption of the clockgeneration circuit in the third, standby mode is at least 90% less thanin the first, full power mode.
 16. The clock generation circuit of claim12 wherein the at least one control input comprises separate first andsecond enable inputs, and wherein the bias circuit is operative tooperate the clock generation circuit in the first, full power mode inresponse to both first and second enable signals received at the firstand second enable inputs, respectively, being asserted; operate theclock generation circuit in the second, sleep mode in response to bothfirst and second enable signals being deasserted; and operating theclock generation circuit in the third, standby mode in response to thefirst enable signal being asserted and the second enable signal beingdeasserted.
 17. The clock generation circuit of claim 11 wherein thebias circuit is operative to operate the clock generation circuit in thefirst, full power mode by providing a first bias current to the clockgeneration circuit; operate the clock generation circuit in the second,sleep mode by providing no bias current to the clock generator circuit;and operate the clock generation circuit in the third, standby mode byproviding a second bias current, less than the first bias current, tothe clock generation circuit.
 18. The clock generation circuit of claim17 wherein the second bias current is about 10% of the first biascurrent or less.
 19. The clock generation circuit of claim 11 whereinthe oscillator circuit is an RC oscillator.
 20. The clock generationcircuit of claim 11 wherein the oscillator circuit is a relaxationoscillator.
 21. A clock generation circuit comprising: an oscillatorcircuit including an amplifier and operative to selectively generate aperiodic signal; a bias circuit connected to the amplifier; and anoutput circuit receiving the periodic signal from the oscillator circuitand operative to output a clock signal; wherein the clock generationcircuit is adapted to operate in one of a first full power mode, asecond sleep mode or a third standby mode, dependent on an indicationprovided for the clock generation circuit; wherein in the first fullpower mode, the oscillator circuit provides the periodic signal to theoutput circuit and the output circuit generates the clock signal; in thesecond sleep mode, the oscillator circuit is disabled; and in the thirdstandby mode, the amplifier is biased to a voltage close to itsamplifier operating voltage but the oscillator circuit does not generatethe periodic signal.
 22. The clock generation circuit of claim 21wherein the oscillator circuit is an RC oscillator circuit and theamplifier is included in the RC oscillator circuit.
 23. The clockgeneration circuit of claim 22 where the oscillator circuit is arelaxation oscillator circuit comprising a current generation circuitconnected to an integration circuit and the amplifier is included in thecurrent generation circuit.
 24. The clock generation circuit of claim 23wherein, in the third standby mode, a first transistor in the currentgeneration circuit is biased to a voltage close to its transistoroperating voltage.
 25. The clock generation circuit of claim 23 wherein,in the first full power mode the first transistor is connected between asecond transistor and a variable resistance unit and in the thirdstandby mode the first transistor is connected between the secondtransistor and a plurality of diodes and wherein, in both the first fullpower mode and the third standby mode, the bias circuit provides a lowbias current to the amplifier circuit.
 26. The clock generation circuitof claim 25 wherein the gate of the second transistor in the currentgeneration circuit is connected in a current mirror arrangement to thegate of a third transistor in the integration circuit of the relaxationoscillator circuit and wherein in the first full power mode, a mirroredcurrent is provided to a capacitor of the relaxation oscillator circuit.27. The clock generation circuit of claim 21 wherein the indicationcomprises a clock request and a standby signal.
 28. The clock generationcircuit of claim 21 further comprising at least one control input toreceive a clock request and a standby signal from a control unit.
 29. Apower management unit comprising a clock generation circuit including:an oscillator circuit including an amplifier and operative toselectively generate a periodic signal; a bias circuit connected to theamplifier; and an output circuit receiving the periodic signal from theoscillator circuit and operative to output a clock signal; wherein theclock generation circuit is adapted to operate in one of a first fullpower mode, a second sleep mode or a third standby mode, dependent on anindication provided for the clock generation circuit; wherein in thefirst full power mode, the oscillator circuit provides the periodicsignal to the output circuit and the output circuit generates the clocksignal; in the second sleep mode, the oscillator circuit is disabled;and in the third standby mode, the amplifier is biased to an amplifiervoltage close to its operating voltage but the oscillator circuit doesnot generate the periodic signal; and a switch mode power supplycircuit; wherein, in the first full power mode, the switch mode powersupply circuit receives the clock signal from the output circuit andprovides power to an electronic circuit.
 30. The power management unitof claim 29 wherein the oscillator circuit is an RC oscillator circuitand the amplifier is included in the RC oscillator circuit.
 31. Thepower management unit of claim 29 where the oscillator circuit is arelaxation oscillator circuit comprising a current generation circuitconnected to an integration circuit and the amplifier is included in thecurrent generation circuit.
 32. A wireless modem comprising a clockgeneration circuit including: an oscillator circuit including anamplifier and operative to selectively generate a periodic signal; abias circuit connected to the amplifier; and an output circuit receivingthe periodic signal from the oscillator circuit and operative to outputa clock signal; wherein the clock generation circuit is adapted tooperate in one of a first full power mode, a second sleep mode or athird standby mode, dependent on an indication provided for the clockgeneration circuit; wherein in the first full power mode, the oscillatorcircuit provides the periodic signal to the output circuit and theoutput circuit generates the clock signal; in the second sleep mode, theoscillator circuit is disabled; and in the third standby mode, theamplifier is biased to an amplifier voltage close to its operatingvoltage but the oscillator circuit does not generate the periodicsignal.
 33. The wireless modem of claim 32 wherein the oscillatorcircuit is an RC oscillator circuit and the amplifier is included in theRC oscillator circuit.
 34. The wireless modem of claim 32 where theoscillator circuit is a relaxation oscillator circuit comprising acurrent generation circuit connected to an integration circuit and theamplifier is included in the current generation circuit.
 35. Thewireless modem of claim 32 further comprising at least one of a digitalbroadband integrated circuit, a radio frequency integrated circuit, anda power amplifier.
 36. A wireless communication terminal comprising aclock generation circuit including: an oscillator circuit including anamplifier and operative to selectively generate a periodic signal; abias circuit connected to the amplifier; and an output circuit receivingthe periodic signal from the oscillator circuit and operative to outputa clock signal; wherein the clock generation circuit is adapted tooperate in one of a first full power mode, a second sleep mode or athird standby mode, dependent on an indication provided for the clockgeneration circuit; wherein in the first full power mode, the oscillatorcircuit provides the periodic signal to the output circuit and theoutput circuit generates the clock signal; in the second sleep mode, theoscillator circuit is disabled; and in the third standby mode, theamplifier is biased to an amplifier voltage close to its operatingvoltage but the oscillator circuit does not generate the periodicsignal.
 37. The wireless communication terminal of claim 36 wherein theoscillator circuit is an RC oscillator circuit and the amplifier isincluded in the RC oscillator circuit.
 38. The wireless communicationterminal of claim 36 where the oscillator circuit is a relaxationoscillator circuit comprising a current generation circuit connected toan integration circuit and the amplifier is included in the currentgeneration circuit.